When the transmission speed of the data increases, the signal integrality becomes the most key factor for the design engineer. Data of this index transmission speed increase and can be observed while all employ, the router from portable mobile device and consumer to the high bandwidth reveals the products / puts through. Nervous (noise) The main reason it is SI level of reducing in a kind of design. Do not realize SI improves technology, impedance matches and the use of the more expensive material by overall arrangement, the design engineer can totally increase nervous eliminators such as the draw of their design. This will allow them to pay close attention to the core of their system and design and not devoted to SI very much.

Simple concepthere of signal of making line that once is not the difference in the sound from a visual angle laid or datum signal in the video. Thus, the signal of making line is seldom a thing cared about. In the era recently, however, this has already totally changed. Video signal now in each road 3.3 Gbps travel, and the data signal is going beyond each road 5 Gbps travel. Like the high-speed continuous standard such as PCIe, XAUI, SATA, TMDS and DisplayPort have already set up a demand to let to design team and engineer to not merely consider the signal integrality, what performance of today’s system of influence and detailed knowledge of the dependability but have it.

The signal is nervous
Knowledge this, engineer must firsth influence SI in the system. Nervous that SI losses observe in adding with the signal of a system. Two kinds of main tense compositions in a system are always tense: Random and decisive. And Gaussian, at the property, decisive to can predict bunch while being tense when tense and boundless at random. In 90% of the system, the decisive intension will be main SI question that the design engineer must manage.

The decisive one is interfered with (ISI) tensely around intersymbol ,The job circulation that causes with the bandwidth is out of shape and limits the question fixedly intensely, clock cycle but also crosses commissure or EMI question asymmetrically, part. Passive component (such as the connector, PCB trace, long cable or other passive components) along the trace To the decisive contribution the most of intension.

One signal until high frequency more decay. That causes a power level to mix in a fixed dataflow by mistake, level of this power is worthy of causing ISI in your signal by mistake. ISI can reduce signal to be integrality enough to prevent receiver from in receive end take real datum any out of the signal.

It is that a design engineer can’t guarantee the design that the data pass through them that the reason is mixed by mistake by the power level. The data may change 100% of the time (0-1-0-1-0-1,etc.) ,Whether or it may be invariable it is not (1-1-1-1-1-1,etc.) of conversion Circulation. Clear, understand, 6 change a little that describe circulation getting little than invariable small stream job that observe. Because job circulation is small 6 x, frequency is big 6 x. And if your dataflow includes two types, because higher frequency will be decayed more, you can have a signal finally with very different power level.

Most high-speed signal standard confirm, can make continuous quantity of a little that does not change reduce to minimumly already, explanation such as 8 byte/10byte code. This code plans to guarantee the dataflow has never exceeded 4 a little not changed continuously. However, it still left an end received which is used in the trace and has a part of 4 x likewise many power and has design engineer that a signal is inclined to.

Mix and reduce ISI in power level by mistake in order to compensate that, the designer can use the equilibrium or weaken technology relatively. Balanced production one power give all high speed promotion a bit. It is similar to the low power level of a little in pace that this enables a little of high speed to have, so enable and reduce to the minimum power level and mix by mistake.

As to weakening, balanced and opposite, there are the same goals too: Make the level mismatch of power reduce to minimumly. This is done through ability to reduce a little of low-speed, however, and the equilibrium increases more high-speed ability. In addition, weakened and only studied a little and balanced a little that only learnt to get conveyed relatively at that time.

This can be used for dispelling decisive tense only technology. Those users will probably have a few needs of telephone transmitter nervous eliminators, for example weaken relatively. To plan to a true tense elimination, two pieces of circuit will be required.

Don’t allow nervous to conciliate, design, this low-cost signal wave form process solution can be offered while being easy. Equilibrate and weaken the circuit to learn and require to dispel relatively tensely with long FR4 trace, the connector and long telegram cause in the design inside, and you needn’t worry understanding the signal integrality improve the detail of technology. Let the tense light and shade boundary line deal with that!

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   August 1st, 2009 at 1:45 am

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